Current approaches to implementing microscale circuitry for computer processors, memory, and other computational machinery have led to spectacular, exponential increases in circuit density and computational power during the past half century. However, the steep, two-fold increase in processing power and feature density every two years that has characterized computer evolution for many years and that is referred to as “Moore's Law,” has begun to flatten, with further decreases feature size now encountering physical limitations and practical constraints, including increasing electrical resistivity as signal lines diminish in size, increasing difficulty in removing heat from processors that produce increasing amounts of heat due to increases in the capacitance of features as feature sizes diminish, higher defect and failure rates in processor and memory components due to difficulties encountered in manufacturing ever smaller features, and difficulties in designing manufacturing facilities and methodologies to further decrease feature sizes. As further reductions in feature sizes within integrated circuits prove increasingly difficult, a variety of alternative approaches to increasing the computational power of integrated-circuit-based electronic devices have begun to be employed. As one example, processor vendors are producing multi-core processors that increase computational power by distributing computation over multiple cores that execute various tasks in parallel. Other efforts include fabricating circuitry at the nanoscale level, using various molecular electronics techniques, and addressing defect and reliability issues by applying theoretical approaches based on information science in similar fashion to the use of error-correcting codes to ameliorate faulty transmission of data signals through electronic communications media. Additional efforts are directed to developing nanoscale circuitry, referred to as “neuromorphic circuitry,” that mimics biological neural circuitry that provides biological organisms with spectacularly efficient, low-power, parallel computational machinery. However, many current approaches employ conventional logic implemented in complementary metal oxide semiconductor (“CMOS”) technologies to implement neuromorphic-circuitry-equivalents to synapses, severely limiting the density at which the neuromorphic-circuitry-equivalents to neurons can be fabricated, generally to a few thousand neurons per square centimeter of semiconductor-chip surface area. Researchers and developers of neuromorphic circuitry have thus recognized that, in order to produce sufficiently dense neuromorphic circuitry, new techniques and new architectures are needed.